This invention relates to semiconductor integrated circuit structures. More particularly, it is concerned with methods of fabricating electrical interconnections between elements of semiconductor integrated circuits.
In semiconductor integrated circuits it is frequently necessary to use two layers of conductive material in the electrical interconnections between elements because no single conductive material has ideal properties. Typically a layer of a first metal provides a thin diffusion barrier which prevents alloying between the semiconductor material and an upper layer of a second metal. Aluminum has been found particularly useful as a conductive material for interconnections on semiconductor integrated circuits. In order to prevent the aluminum from alloying with the semiconductor material and possibly causing short-circuits through shallow junctions, an underlaying layer of a diffusion barrier material, for example tungsten, is provided between the semiconductor material and the aluminum. Fabricating electrical interconnections of two layers of metal is more complex since the metal etching process must be carried out in two steps rather than one.
Difficulty is frequently encountered in precisely defining elements of an integrated circuit structure when the surface of the structure is irregular by virtue of the presence of several layers of different materials disposed on various portions of the semiconductor body. In order to correct for the unevenness of the surface, particularly when employing photographic techniques to define elements, planarizing material is placed over the structure in order to provide a more nearly planar upper surface. The layer of planarizing material is covered with a thin sputtered layer of silicon, and a conventional photoresist material is applied over the silicon layer. Standard photolithographic techniques are employed to form openings in the photoresist material, and the sputtered silicon layer is etched to produce openings therein, defined by the openings in the photoresist material. The silicon layer then serves as a mask for etching openings in the planarizing material and in the underlying integrated circuit structure. This procedure is known as the tri-level resist technique and is widely used in the semiconductor industry.
In fabricating electrical interconnections of two layers of metal on an integrated circuit structure, the tri-level resist technique is employed to form openings in the adherent protective coating to expose contact areas. The masking materials are removed. The first and then the second metal of the two-layer interconnections are deposited over the structure. The tri-level resist technique is repeated to define the desired pattern of electrical connections by exposing the metal which is to be removed. The unwanted upper metal is removed and then the exposed unwanted lower metal is removed in a two-step etching process leaving the desired pattern of interconnections.